1. Field of the Invention
The present invention relates to methods for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a field effect transistor.
2. Description of Related Art
A damascene process is known as an interconnect forming method in a method for manufacturing a semiconductor device.
In the damascene process, for example, a gate electrode trench is formed in an insulating film over a substrate, and an electrically-conductive material is so deposited as to fill the inside of the gate electrode trench. Subsequently, chemical mechanical polishing (CMP) treatment or the like is performed to thereby remove the conductive material outside the gate electrode trench while leaving the conductive material in the gate electrode trench, so that the left conductive material will be used as an interconnect.
Miniaturization of a metal-oxide-semiconductor field effect transistor (MOSFET, hereinafter referred to as a MOS transistor), which is a basic element in a semiconductor device, is being advanced along with the progression of miniaturization and integration degree enhancement of semiconductor devices. Thus, the thickness of the gate insulating film as well as the gate length needs to be decreased in accordance with the scaling rule.
Although a SiON insulating film is often used as the gate insulating film, it is difficult to use the SiON insulating film as the gate insulating film for the 32-nm generation and subsequent generations because large leakage will arise.
To address this problem, studies are being made on a method in which a high dielectric constant film (so-called High-k film), which allows large physical thickness, is used as the material of the gate insulating film.
Typically, the heat resistance of the High-k film is low, and therefore the gate insulating film formed of the High-k film needs to be formed after thermal diffusion treatment for the source and drain regions, which requires a high temperature.
As a method permitting such a procedure, a damascene gate process is known, in which the gate electrode of a MOS transistor is formed by using the above-described damascene process.
Methods of forming a MOS transistor by using the damascene gate process are disclosed in Japanese Patent Laid-open No. 2005-303256, PCT Patent Publication No. WO2001/097943, and Japanese Patent Laid-open No. 2001-308318.
One example of a manufacturing method based on the damascene gate process will be described below.
Initially, steps until the structure shown in FIG. 10A is obtained will be described.
For example, in a silicon semiconductor substrate 100 having a channel forming region, an element-isolation insulating film 101 for separating active regions is formed by shallow trench isolation (STI).
Subsequently, silicon oxide is formed over the entire surface by e.g. thermal oxidation, and poly-silicon is deposited by chemical vapor deposition (CVD). Furthermore, silicon nitride is deposited. Subsequently, etching processing is carried out by photolithography for the entire surface except for the gate forming region, to thereby stack a dummy gate insulating film 102 composed of silicon oxide, a dummy gate electrode 103 composed of poly-silicon, and a hard mask layer 104 composed of silicon nitride over the gate electrode forming region in the active region of the semiconductor substrate 100.
Next, for example, offset spacers 105 are formed on both the sides of the dummy gate electrode 103 by depositing silicon nitride over the entire surface by CVD and performing etch-back for the entire surface.
Next, for example, pocket layers (not shown) and extension regions 106 are formed in the semiconductor substrate 100 by ion-implantation of an impurity into the active region with use of the offset spacers 105 and the hard mask layer 104 as the implantation mask.
Subsequently, for example, silicon nitride is deposited over the entire surface by plasma CVD and silicon oxide is deposited, followed by etch-back for the entire surface. Thereby, sidewall spacers formed of a silicon nitride film 107a and a silicon oxide film are formed on both the sides of the offset spacers 105.
Next, for example, source and drain regions 109 are formed in the semiconductor substrate 100 by ion-implantation of an impurity into the active region with use of the sidewall spacers, the offset spacers 105, and the hard mask layer 104 as the implantation mask.
Thereafter, the resist film is separated, and the silicon oxide film as a part of the sidewall spacers and the other exposed silicon oxide film are removed by diluted hydrofluoric acid (DHF) treatment. Furthermore, thermal treatment such as spike rapid thermal annealing (RTA) treatment (1050° C.) is carried out for activation of the impurities.
Subsequently, for example, a refractory metal such as cobalt is deposited by sputtering over the entire surface, and silicidation across the interface between the silicon and the refractory metal on the surface of the source and drain regions is caused by RTA treatment, so that a refractory metal silicide layer 110 is formed. Thereafter, the unreacted refractory metal is removed.
Through the above-described steps, the structure shown in FIG. 10A is obtained.
Although the silicon oxide film as a part of the sidewall spacers is removed by the above-described DHF treatment, the component formed only of the silicon nitride film 107a will also be often referred to as the sidewall spacer, hereinafter.
Referring next to FIG. 10B, for example, silicon oxide is so deposited by CVD over the entire surface that the sidewall spacers, the offset spacers 105, and the hard mask layer 104 are covered, to thereby form a first interlayer insulating film 111.
Next, as shown in FIG. 11A, polishing is carried out by chemical mechanical polishing (CMP) from the top surface side until the surface of the dummy gate electrode 103 is exposed.
Subsequently, as shown in FIG. 11B, for example, the dummy gate electrode 103 and the dummy gate insulating film 102 are removed by etching treatment under a predetermined condition. Due to this step, a gate electrode trench T is formed in the part in which the dummy gate electrode 103 and the dummy gate insulating film 102 existed.
The above-described etching includes a step of removing the dummy gate electrode composed of silicon oxide by etching. Therefore, the first interlayer insulating film 111 composed of silicon oxide is etched from its surface and thus the surface level thereof lowers toward the semiconductor substrate 100.
Subsequently, as shown in FIG. 12A, for example, a gate insulating film 113 composed of hafnium oxide or the like is so formed over the entire surface as to cover the inside of the gate electrode trench T by atomic layer deposition (ALD).
Next, for example, an electrically-conductive layer 114 is formed by depositing tungsten or the like on the gate insulating film 113 across the entire surface by sputtering, CVD, or the like in such a manner as to fill the gate electrode trench T.
Subsequently, as shown in FIG. 12B, for example, polishing or the like is performed from the top surface of the conductive layer 114 to thereby remove the conductive layer 114 deposited outside the gate electrode trench T, so that a gate electrode 114a is formed in the gate electrode trench T.
As a result of this step, because the surface level of the first interlayer insulating film 111 has lowered as described above, a conductive layer residue 114r and a gate insulating film residue 113r are left outside the gate electrode trench T and above the source and drain regions 109.
Subsequently, as shown in FIG. 13A, for example, a second interlayer insulating film 115 is formed by depositing silicon oxide over the entire surface by CVD. Next, as shown in FIG. 13B, opening of contact holes CH that reach the source and drain regions is attempted. However, because the conductive layer residue 114r is left above the source and drain regions 109 as described above, the opening of the contact holes finishes at the timing when the contact holes reach the conductive layer residue 114r. 
Furthermore, the conductive layer residue 114r will cause short-circuiting.